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February 1996
NDS8410 Single N-Channel Enhancement Mode Field Effect Transistor
General Description
These N-Channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance and provide superior switching performance. These devices are particularly suited for low voltage applications such as notebook computer power management and other battery powered circuits where fast switching, low in-line power loss, and resistance to transients are needed.
Features
10A, 30V. RDS(ON) = 0.015 @ VGS = 10V RDS(ON) = 0.020 @ VGS = 4.5V. High density cell design for extremely low RDS(ON). High power and current handling capability in a widely used surface mount package.
____________________________________________________________________________________________
5
6 7 8
4 3 2
1
Absolute Maximum Ratings
Symbol VDSS VGSS ID PD Parameter Drain-Source Voltage Gate-Source Voltage Drain Current - Continuous - Pulsed
T A = 25C unless otherwise noted
NDS8410 30 20
(Note 1a)
Units V V A
10 50
Maximum Power Dissipation
(Note 1a) (Note 1b) (Note 1c)
2.5 1.2 1 -55 to 150
W
TJ,TSTG
Operating and Storage Temperature Range
C
THERMAL CHARACTERISTICS RJA RJC Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Case
(Note 1a) (Note 1)
50 25
C/W C/W
(c) 1997 Fairchild Semiconductor Corporation
NDS8410 Rev B2
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)
Symbol Parameter Conditions Min Typ Max Units OFF CHARACTERISTICS BVDSS IDSS IGSSF IGSSR VGS(th) RDS(ON) ID(on) gFS Ciss Coss Crss tD(on) tr tD(off) tf Qg Qgs Qgd Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current VGS = 0 V, ID = 250 A VDS = 24 V, VGS = 0 V TJ= 55C Gate - Body Leakage, Forward Gate - Body Leakage, Reverse VGS = 20 V, VDS = 0 V VGS = -20 V, VDS= 0 V VDS = VGS, ID = 250 A VGS = 10 V, ID = 10 A VGS = 4.5 V, ID = 9 A On-State Drain Current Forward Transconductance VGS = 10 V, VDS = 5 V VDS = 10 V, ID = 10 A VDS = 15 V, VGS = 0 V, f = 1.0 MHz 20 22 1 1.5 0.013 0.018 0.015 0.02 A S 30 1 10 100 -100 V A A nA nA
ON CHARACTERISTICS (Note 2) Gate Threshold Voltage Static Drain-Source On-Resistance V
DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance 1350 800 300 pF pF pF
SWITCHING CHARACTERISTICS (Note 2) Turn - On Delay Time Turn - On Rise Time Turn - Off Delay Time Turn - Off Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge VDS = 15 V, ID = 10 A, VGS = 10 V VDD = 10 V, ID = 1 A, VGEN = 10 V, RGEN = 6 14 20 56 31 46 5.6 14 30 25 100 80 60 ns ns ns ns nC nC nC
NDS8410 Rev B2
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)
Symbol Parameter Conditions Min Typ Max 2.1
(Note 2)
Units A V ns
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS IS VSD trr
Notes: 1. RJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RJC is guaranteed by design while RCA is determined by the user's board design.
Maximum Continuous Drain-Source Diode Forward Current Drain-Source Diode Forward Voltage Reverse Recovery Time VGS = 0 V, IS = 10 A 0.8
1.2 80
VGS = 0V, IF = 2.1 A, dIF/dt = 100 A/s
PD(t) =
R J A (t)
T J-TA
=
R J C CA +R (t)
T J-TA
= I 2 (t) x RDS (ON ) D
TJ
Typical RJA using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment: a. 50oC/W when mounted on a 1 in2 pad of 2oz copper. b. 105oC/W when mounted on a 0.04 in2 pad of 2oz copper. c. 125oC/W when mounted on a 0.006 in2 pad of 2oz copper.
1a
1b
1c
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300s, Duty Cycle < 2.0%.
NDS8410 Rev B2
Typical Electrical Characteristics
50 3
VGS =10V 6.0 5.0
I D , DRAIN-SOURCE CURRENT (A)
40
4.0
R DS(on), NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
4.5
V GS = 3.0V
2.5
3.5
2
30
3.5
4.0 4.5
1.5
20
5.0 6.0 10
3.0
10
1
2.5
0 0 0.5 1 1.5 2 VDS , DRAIN-SOURCE VOLTAGE (V) 2.5 3 0.5 0 10 20 30 I D , DRAIN CURRENT (A) 40 50
Figure 1. On-Region Characteristics.
Figure 2. On-Resistance Variation with Drain Current and Gate Voltage.
1.6
2
R DS(ON), NORMALIZED
R DS(on) , NORMALIZED
1.4
V GS = 10V
DRAIN-SOURCE ON-RESISTANCE
DRAIN-SOURCE ON-RESISTANCE
I D = 10A
V GS = 10 V
1.5
TJ = 125C
1.2
1
1
25C -55C
0.8
0.6 -50
0.5 -25 0 25 50 75 100 125 150 0 10 I D T J , JUNCTION TEMPERATURE (C) 20 30 , DRAIN CURRENT (A) 40 50
Figure 3. On-Resistance Variation with Temperature.
Figure 4. On-Resistance Variation with Drain Current and Temperature.
40
1.4
V DS = 10V
I D , DRAIN CURRENT (A)
30
TJ = -55C
125C 25C
V th, NORMALIZED
GATE-SOURCE THRESHOLD VOLTAGE
1.2
V DS = V GS I D = 250A
1
20
0.8
10
0.6
0 1 2 3 4 V GS , GATE TO SOURCE VOLTAGE (V) 5
0.4 -50
-25
0 25 50 75 100 T J , JUNCTION TEMPERATURE (C)
125
150
Figure 5. Transfer Characteristics.
Figure 6. Gate Threshold Variation with Temperature.
NDS8410 Rev B2
Typical Electrical Characteristics (continued)
DRAIN-SOURCE BREAKDOWN VOLTAGE
1.12
IS , REVERSE DRAIN CURRENT (A)
20
I D = 250A
10 5
V G S = 0V
1.08
BV DSS , NORMALIZED
1 0.5
TJ = 125C 25C -55C
1.04
0.1
1
0.96
0.01
0.92 -50
-25
0 25 50 75 100 T J , JUNCTION TEMPERATURE (C)
125
150
0.001 0.2
0.4 0.6 0.8 1 VSD , BODY DIODE FORWARD VOLTAGE (V)
1.2
Figure 7. Breakdown Voltage Variation with Temperature.
Figure 8. Body Diode Forward Voltage Variation with Source Current and Temperature.
4000
10
I D = 10A
, GATE-SOURCE VOLTAGE (V) 2000 CAPACITANCE (pF) 8
V DS = 10V
20V
C iss
1000 800
15V
6
C oss
4
500
f = 1 MHz
300 200 0.1
V 0 0.2 0.5 1 2 5 10 30 0 10 20 30 40 50 V DS , DRAIN TO SOURCE VOLTAGE (V) Q g , GATE CHARGE (nC)
Figure 9. Capacitance Characteristics.
GS
V GS = 0 V
C rss
2
Figure 10. Gate Charge Characteristics.
VDD
t d(on)
t on
t off tr
90%
t d(off)
90%
V IN
D
RL V OUT
VOUT
10%
tf
VGS
R GEN
10%
INVERTED
G
DUT 90% S
V IN
10%
50%
50%
PULSE WIDTH
Figure 11. Switching Test Circuit.
Figure 12. Switching Waveforms.
NDS8410 Rev B2
Typical Electrical and Thermal Characteristics (continued)
2.5 STEADY-STATE POWER DISSIPATION (W)
40
V DS = 10V
, TRANSCONDUCTANCE (SIEMENS) 32
1a
T J = -55C 25C
2
24
125C
1.5
1b 1c
16
1
4.5"x5" FR-4 Board TA = 2 5 C Still Air
o
8
g
FS
0 0 5 10 15 I D , DRAIN CURRENT (A) 20 25
0.5 0 0.2 0.4 0.6 0.8 2oz COPPER MOUNTING PAD AREA (in 2 ) 1
Figure 13. Transconductance Variation with Drain Current and Temperature.
Figure 14. SO-8 Maximum Steady-State Power Dissipation versus Copper Mounting Pad Area.
11 I D , STEADY-STATE DRAIN CURRENT (A)
100 50 30 10 ID , DRAIN CURRENT (A) 5
(O N) LIM IT
10 1m 10 10 ms s
0u
10
1a
S RD
s
s
9
1 0.3 0.1 0.03
0m
8
1b 1c 4.5"x5" FR-4 Board TA = 2 5 o C Still Air VG S = 1 0 V
V GS = 10V SINGLE PULSE R J A = See Note 1c T A = 25C
0.2 0.5 1 2
1s 10 s DC
7
6 0
0.2 0.4 0.6 0.8 2oz COPPER MOUNTING PAD AREA (in 2 )
1
0.01 0.1
5
10
30
50
V DS , DRAIN-SOURCE VOLTAGE (V)
Figure 15. Maximum Steady- State Drain Current versus Copper Mounting Pad Area.
1 0 .5 TRANSIENT THERMAL RESISTANCE
r(t), NORMALIZED EFFECTIVE
D = 0.5 0.2 0.1 0.05 0.02 0.01 Single Pulse
Figure 16. Maximum Safe Operating Area.
0 .2 0 .1 0 .0 5 0 .0 2 0 .0 1 0 .0 0 5 0 .0 0 2 0 .0 0 1 0 .0001
R JA (t) = r(t) * R JA R JA = See Note 1c
P(pk)
t1 TJ - T
t2
= P * R JA (t) Duty Cycle, D = t 1 / t 2
A
0 .001
0 .0 1
0 .1
1
10
100
300
t 1 , TIME (sec)
Figure 17. Transient Thermal Response Curve.
Note: Thermal characterization performed using the conditions described in note 1c. Transient thermal response will change depending on the circuit board design.
NDS8410 Rev B2
SO-8 Tape and Reel Data and Package Dimensions
SOIC(8lds) Packaging Configuration: Figure 1.0
Packaging Description:
EL ECT ROST AT IC SEN SIT IVE DEVICES
DO NO T SHI P OR STO RE N EAR ST RO NG EL ECT ROST AT IC EL ECT RO M AGN ETI C, M AG NET IC O R R ADIO ACT IVE FI ELD S
TNR D ATE PT NUMB ER PEEL STREN GTH MIN ___ __ ____ __ ___gms MAX ___ ___ ___ ___ _ gms
Antistatic Cover Tape
ESD Label
SOIC-8 parts are shipped in tape. The carrier tape is made from a dissipative (carbon filled) polycarbonate resin. The cover tape is a multilayer film (Heat Activated Adhesive in nature) primarily composed of polyester film, adhesive layer, sealant, and anti-static sprayed agent. These reeled parts in standard option are shipped with 2,500 units per 13" or 330cm diameter reel. The reels are dark blue in color and is made of polystyrene plastic (antistatic coated). Other option comes in 500 units per 7" or 177cm diameter reel. This and some other options are further described in the Packaging Information table. These full reels are individually barcode labeled and placed inside a standard intermediate box (illustrated in figure 1.0) made of recyclable corrugated brown paper. One box contains two reels maximum. And these boxes are placed inside a barcode labeled shipping box which comes in different sizes depending on the number of parts shipped.
Static Dissipative Embossed Carrier Tape
F63TNR Label Customized Label
F852 NDS 9959 F852 NDS 9959 F852 NDS 9959 F852 NDS 9959
SOIC (8lds) Packaging Information Packaging Option Packaging type Qty per Reel/Tube/Bag Reel Size Box Dimension (mm) Max qty per Box Weight per unit (gm) Weight per Reel (kg) Note/Comments Standard (no flow code) TNR 2,500 13" Dia 343x64x343 5,000 0.0774 0.6060 L86Z Rail/Tube 95 530x130x83 30,000 0.0774 F011 TNR 4,000 13" Dia 343x64x343 8,000 0.0774 0.9696 D84Z TNR 500 7" Dia 184x187x47 1,000 0.0774 0.1182
F852 NDS 9959
Pin 1
SOIC-8 Unit Orientation
343mm x 342mm x 64mm Standard Intermediate box ESD Label F63TNR Label sample
LOT: CBVK741B019 FSID: FDS9953A QTY: 2500 SPEC:
F63TNLabel F63TN Label ESD Label
(F63TNR)3
D/C1: D9842 D/C2:
QTY1: QTY2:
SPEC REV: CPN: N/F: F
SOIC(8lds) Tape Leader and Trailer Configuration: Figure 2.0
Carrier Tape Cover Tape
Components Trailer Tape 640mm minimum or 80 empty pockets Leader Tape 1680mm minimum or 210 empty pockets
July 1999, Rev. B
SO-8 Tape and Reel Data and Package Dimensions, continued
SOIC(8lds) Embossed Carrier Tape Configuration: Figure 3.0
T E1
P0
D0
F K0 Wc B0 E2 W
Tc A0 P1 D1
User Direction of Feed
Dimensions are in millimeter Pkg type SOIC(8lds) (12mm)
A0
6.50 +/-0.10
B0
5.30 +/-0.10
W
12.0 +/-0.3
D0
1.55 +/-0.05
D1
1.60 +/-0.10
E1
1.75 +/-0.10
E2
10.25 min
F
5.50 +/-0.05
P1
8.0 +/-0.1
P0
4.0 +/-0.1
K0
2.1 +/-0.10
T
0.450 +/0.150
Wc
9.2 +/-0.3
Tc
0.06 +/-0.02
Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/Jedec RS-481 rotational and lateral movement requirements (see sketches A, B, and C).
20 deg maximum Typical component cavity center line
0.5mm maximum
B0 20 deg maximum component rotation
0.5mm maximum
Sketch A (Side or Front Sectional View)
Component Rotation
A0 Sketch B (Top View)
Typical component center line
Sketch C (Top View)
Component lateral movement
SOIC(8lds) Reel Configuration: Figure 4.0
Component Rotation
W1 Measured at Hub
Dim A Max
Dim A max
Dim N
See detail AA
7" Diameter Option
B Min Dim C See detail AA W3
Dim D min
13" Diameter Option
W2 max Measured at Hub DETAIL AA
Dimensions are in inches and millimeters
Tape Size
12mm
Reel Option
7" Dia
Dim A
7.00 177.8 13.00 330
Dim B
0.059 1.5 0.059 1.5
Dim C
512 +0.020/-0.008 13 +0.5/-0.2 512 +0.020/-0.008 13 +0.5/-0.2
Dim D
0.795 20.2 0.795 20.2
Dim N
2.165 55 7.00 178
Dim W1
0.488 +0.078/-0.000 12.4 +2/0 0.488 +0.078/-0.000 12.4 +2/0
Dim W2
0.724 18.4 0.724 18.4
Dim W3 (LSL-USL)
0.469 - 0.606 11.9 - 15.4 0.469 - 0.606 11.9 - 15.4
12mm
13" Dia
(c) 1998 Fairchild Semiconductor Corporation
July 1999, Rev. B
SO-8 Tape and Reel Data and Package Dimensions, continued
SOIC-8 (FS PKG Code S1)
1:1
Scale 1:1 on letter size paper
Dimensions shown below are in: inches [millimeters]
Part Weight per unit (gram): 0.0774
9
September 1998, Rev. A
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No Identification Needed
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This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.

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